The present subject matter relates to a semiconductor design technology, and more particularly, to a semiconductor memory device for generating a main strobe signal as a source signal for columns and a driving method thereof.
In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) generates a main strobe signal in response to a column address strobe (CAS) which is a column command. The main strobe signal is a pulse signal having a pulse width corresponding to an external clock signal. Such a main strobe signal is used as a source signal for generating main signals for columns. The main strobe signal is mainly used to generate a column selection signal, a write driver enable signal, and an input/output sense amplifying enable signal. Here, the column selection signal, the write driver enable signal, and the input/output sense amplifying enable signal have a pulse width corresponding to the main strobe signal.
FIG. 1 illustrates an operation waveform of a semiconductor memory device according to the related art. FIG. 1 shows a main strobe signal STB_MN, an address information ADD, main/sub local input/output lines LIO and LIOb, and a column selection signal YI.
Referring to FIG. 1, the main strobe signal STB_MN is activated in response to a column command (not shown), and the column selection signal YI is generated based on the main strobe signal STB_MN. Data corresponding to the address information ADD is applied to the main/sub local input/output lines LIO and LIOb in response to the column selection signal YI. The main local input/output line LIO and the sub local input/output line LIOb sustain a precharge voltage before the column selection signal YI is activated. If the column selection signal YI is activated, a voltage level difference is generated according to applied data. If the column selection signal YI is inactivated, the main local input/output line LIO and the sub local input/output line LIOb sustain the precharge voltage again.
It is assumed that CAS to CAS Delay (tCCD) is equivalent to 2tCK for convenience where tCCD is a minimum time for accessing another column after accessing one column in the same bank. It means that the address information ADD is toggled once at 2tCK. In consideration of the precharging time of the main/sub local input/output lines LIO and LIOb, it is obvious that the column selection signal YI has a pulse width of 1tCK. That is, the main strobe signal STB_MN has the pulse width of 1tCK. Since a skew may be generated at the address information ADD, a window of the address information ADD is not substantially equivalent to 2tCK. Therefore, an operation margin of the address information ADD and the main strobe signal STB_MN is very small.
As a result, next data information ADD is unintentionally reflected although the voltage level difference is not generated in the main/sub local input/output lines LIO and LIOb due to the data. Therefore, it makes reading data difficult. Accordingly, the write driver enable signal and the input/output sense amplifying enable signal which are generated based on the main strobe signal STB_MN also have the operation margin problem.
Since one cycle of an external clock signal applied to a semiconductor memory device is shortened up to 1 nano second (ns) lately, a pulse width of the main strobe signal STB_MN is 500 pico second (ps) to 1 nano second (ns). Accordingly, a pulse width of the column selection signal YI generated corresponding to the main strobe signal STB_MN also becomes shortened. It cannot guarantee enough time for generating sufficient voltage level difference at the main/sub local input/output lines LIO and LIOb. The main strobe signal having a very small pulse width may be unable to make full swing to a destination because the main strobe signal STB_MN has very large loading. Therefore, the operation characteristic of a circuit may be deteriorated. In the worst case, an operation error is caused because the main strobe signal STB_MN disappears.